Appendix. Device Resources

The following lists show important hardware details of all supported hardware platforms of this VisualApplets version. For a detailed list, please check the data sheet of the individual product.

Hardware Configuration of Supported Platforms

Hardware Configuration microEnable IV and PixelPlant:

Resource mE4VD1-CL/-PoCL mE4VD4-CL/-PoCL mE4VQ4-GE/-GPoE px100 px200/px200e
Vision Processor Xilinx Spartan 3 XC3S1600e FPGA Xilinx Spartan 3 XC3S4000 FPGA Xilinx Spartan 3 XC3S4000 FPGA Xilinx Spartan 3 XC3S1600e FPGA Xilinx Spartan 3 XC3S4000 FPGA
LUT 29504 55296 55296 29504 55296
FlipFlop 29504 55296 55296 29504 55296
Block RAM* 36 à 18432Bit 96 à 18432Bit 96 à 18432Bit 36 à 18432Bit 96 à 18432Bit
Embedded Arithmetic Logic Unit (ALU)* 36 96 96 36 96
RAM 2 x 128MiB DDR 4 x 128MiB DDR 4 x 128MiB DDR 2 x 128MiB DDR 4 x 128MiB DDR
Data Width per RAM 64Bit 64Bit 64Bit 64Bit 64Bit
Bandwidth per RAM 1GB/s 1GB/s 1GB/s 1GB/s 1GB/s
Base Design Clock 62.5MHz 62.5MHz 62.5MHz 62.5MHz 62.5MHz
Host Interface PCIe x1 PCIe x4 PCIe x4 - -
Host Interface (PCIe x 4 Gen 2) Bandwidth (theor.) 250 Mbyte/s per direction on PCIe bus 1 Gbyte/s per direction on PCIe bus 1 Gbyte/s per direction on PCIe bus - -
Host Interface (PCIe x 4 Gen 2) Bandwidth (typ./max.) 200 Mbyte/s 750 Mbyte/s / 900 MByte/s 750 Mbyte/s - -

* microEnable IV and PixelPlant only: Block RAM and hardware multiplier are shared. The given value is the total value.

Table 40. Hardware Configuration microEnable IV and PixelPlant


Hardware Configuration microEnable 5 ironman:

Resource mE5VD8-PoCL mE5VQ8-CXP6B/mE5VQ8-CXP6D
Vision Processor Xilinx Virtex6 XC6VLX240T FPGA Xilinx Virtex6 XC6VLX240T FPGA
LUT 150720 150720
FlipFlop 301440 301440
Block RAM 832 x 18432Bit 832 x 18432Bit
Embedded Arithmetic Logic Unit (DSP48) 768 768
RAM 4 x 256MiB DDR3 4 x 256MiB DDR3
Data Width per RAM 128Bit 128Bit
Bandwidth per RAM 4GB/s 3.2GB/s
Base Design Clock 125MHz 125MHz
Host Interface PCIe x8 Gen2 PCIe x8 Gen2
Host Interface (PCIe x 8 Gen 2) Bandwidth (theor.) 4 Gbyte/s per direction on PCIe bus 4 Gbyte/s per direction on PCIe bus
Host Interface (PCIe x 8 Gen 2) Bandwidth (typ./max.) up to 3.6 GByte/s on PCIe bus up to 3.6 GByte/s on PCIe bus

Table 41. Hardware Configuration microEnable 5 ironman


Hardware Configuration LightBridge and microEnable 5 marathon:

Resource mE5 marathon VCX-QP mE5 marathon VF2 mE5 marathon VCL mE5 marathon VCLx LightBridge 2 VCL
Vision Processor Xilinx Kintex7 XC7K160T - 2FFG676C FPGA Xilinx Kintex7 XC7K160T - 2FFG676C FPGA Xilinx Kintex7 XC7K160T - 1FBG676C FPGA Xilinx Kintex7 XC7K410T - 1FBG676C FPGA Xilinx Kintex7 XC7K160T - 1FBG676C FPGA
LUT 101400 101400 101400 254200 101400
FlipFlop 202800 202800 202800 508400 202800
Block RAM 650 x 18kbit 650 x 18kbit 650 x 18kbit 1590 x 18kbit 650 x 18kbit
Embedded Arithmetic Logic Unit (DSP48) 600 600 600 1540 600
RAM size 4 x 512MiB DDR3 4 x 512MiB DDR3 4 x 512MiB DDR3 4 x 512MiB DDR3 4 x 512MiB DDR3
RAM Data Width 512 Bit 512 Bit 256 Bit 256 Bit 256 Bit
RAM Bandwidth total (shared) 12.8 GB/s* 12.8 GB/s* 6.4 GB/s* 6.4 GB/s* 6.4 GB/s*
Base Design Clock (default) 125MHz 125MHz 125MHz 125MHz 125MHz
Base Design Clock (maximal) 312.5 MHz** 312.5 MHz** 312.5 MHz** 312.5 MHz** 312.5 MHz**
Host Interface PCIe x 4 Gen 2 (Direct Memory Access) PCIe x 4 Gen 2 (Direct Memory Access) PCIe x 4 Gen 2 (Direct Memory Access) PCIe x 4 Gen 2 (Direct Memory Access) PCIe x 4 Gen 2 interface via Thunderbolt™ 2 technology
Host Interface (PCIe x 4 Gen 2) Bandwidth (theor.) 1x2000 MB/s 1x2000 MB/s 1x2000 MB/s 1x2000 MB/s 1x2000 MB/s
Host Interface (PCIe x 4 Gen 2) Bandwidth (typ./max.) Up 1800 MB/s sustainable data bandwidth Up to 1800 MB/s sustainable data bandwidth Up to 1800 MB/s sustainable data bandwidth Up to 1800 MB/s sustainable data bandwidth Up to 1400 MB/s sustainable data bandwidth

* The platforms own only one single physical RAM bank which is formatted as 4 independent, non-overlapping memory regions. Though the memory itself is exclusive for each RAM based operator, the RAM bandwidth is shared. See section Shared Memory Concept.

** These platforms allow to use a user-specified base clock. The minimum clock frequency is 125 MHz. Theoretical maximum is 312.5 MHz. Designs with a clock frequency of 125 MHz are likely to meet the timing constraints. Designs with a clock frequency above 125 MHz may result in timing constraints violations.

Table 42. Hardware Configuration LightBridge and microEnable 5 marathon


Device Resources of Supported Platforms

The device resources are limited for each hardware device. The following lists show the available device resources of the supported hardware platforms. Operators use device resources. Each resource can only be used once.

Device resources are allocated either

  • automatically,
  • using operator parameters, or
  • in the Resources dialog.

See 'Allocation of Device Resources' for more information.

_

Device Resources microEnable IV and PixelPlant:

Resource mE4VD1-CL/-PoCL mE4VD4-CL/-PoCL mE4VQ4-GE/-GPoE px100 px200/px200e
CAM 2 2 4
CameraControl 2 2
DMA 8 8 8
Event 64 64
EventSource 14 14
RAM 2 x 128MiB 4 x 128MiB 4 x 128MiB 2 x 128MiB 4 x 128MiB
RxLink 60 60 60 60 60
TriggerOut* 8 8 8 8 8
TxLink 60 60 60 60 60
SignalChannel** 4000 4000 4000 4000 4000
ImageChannel*** 1024 1024 1024 1024 1024

* This resource is not visible in the Resources dialog. It is controlled via operators.

** Resource SignalChannel allows to connect TxSignalLink operators with RxSignalLink operators. Each operator TxSignalLink needs one resource SignalChannel exclusively. Multiple operators RxSignalLink can use the same resource SignalChannel, i.e., multiple operators RxSignalLink can receive the signals transmitted by one operator TxSignalLink. A maximum of 4000 TxSignalLink operators can be used in a design. The number of RxSignalLink operators is not restricted. Resource SignalChannel is visible in the Resources dialog.

*** Resource ImageChannel allows to connect TxImageLink operators with RxImageLink operators. Each operator TxImageLink needs one resource ImageChannel exclusively. Each resource ImageChannel can be connected to exactly one operator RxImageLink, i.e., a maximum of 1024 TxImageLink and 1024 RxImageLink operators can be used in one design. Resource ImageChannel is visible in the Resources dialog.

Table 43. List of Device Resources microEnable IV and PixelPlant


Device Resources microEnable 5 ironman:

Resource mE5VD8-PoCL mE5VQ8-CXP6D/mE5VQ8-CXP6B
Camera Port 2 4
DMARd 4 4
GPO* 8 OUT 8 OUT
RAM 4 x 256MiB 4 x 256MiB
LED Ports* 4 4
GPI** 8 8
SignalChannel*** 4000 4000
EventPort**** 12 14
EventID**** 64 64
ImageChannel***** 1024 1024

* These resources are not visible in the Resources dialog. They are controlled via operators.

** GPI is not visible in the Resources dialog. The same resource can be used multiple times. The table lists the amount of GPI ports.

*** Resource SignalChannel allows to connect TxSignalLink operators with RxSignalLink operators. Each operator TxSignalLink needs one resource SignalChannel exclusively. Multiple operators RxSignalLink can use the same resource SignalChannel, i.e., multiple operators RxSignalLink can receive the signals transmitted by one operator TxSignalLink. A maximum of 4000 TxSignalLink operators can be used in a design. The number of RxSignalLink operators is not restricted. Resource SignalChannel is visible in the Resources dialog.

**** EventID stands for maximal amount of events supported by the software for the particular platform. EventPort represents the event channel. One event channel can host up to 16 events.

***** Resource ImageChannel allows to connect TxImageLink operators with RxImageLink operators. Each operator TxImageLink needs one resource ImageChannel exclusively. Each resource ImageChannel can be connected to exactly one operator RxImageLink, i.e., a maximum of 1024 TxImageLink and 1024 RxImageLink operators can be used in one design. Resource ImageChannel is visible in the Resources dialog.

Table 44. List of Device Resources microEnable 5 ironman


Device Resources LightBridge and microEnable 5 marathon:

Resource mE5 marathon VCX-QP mE5 marathon VF2 mE5 marathon VCL mE5 marathon VCLx LightBridge VCL
Camera Port 4 2 2 2 2
CameraControl - - 2 2 2
DMA 4 4 4 4 4
GPO* 10 OUT 10 OUT 10 OUT 10 OUT 6 OUT
GPI** 12 IN 12 IN 12 IN 12 IN 8 IN
RAM 4 x 512 MiB 4 x 512 MiB 4 x 512 MiB 4 x 512 MiB 4 x 512 MiB
LED Ports* 4 4 2 2 2
SignalChannel*** 4000 4000 4000 4000 4000
EventPort**** 14 14 10 10 10
EventID**** 64 64 64 64 64
ImageChannel***** 1024 1024 1024 1024 1024

* These resources are not visible in the Resources dialog. They are controlled via operators.

** GPI is not visible in the Resources dialog. The same resource can be used multiple times. The table lists the amount of GPI ports.

*** Resource SignalChannel allows to connect TxSignalLink operators with RxSignalLink operators. Each operator TxSignalLink needs one resource SignalChannel exclusively. Multiple operators RxSignalLink can use the same resource SignalChannel, i.e., multiple operators RxSignalLink can receive the signals transmitted by one operator TxSignalLink. A maximum of 4000 TxSignalLink operators can be used in a design. The number of RxSignalLink operators is not restricted. Resource SignalChannel is visible in the Resources dialog.

**** "EventID" stands for maximal amount of events supported by the software for the particular platform. "EventPort" represents the event channel. One event channel can host up to 16 events.

***** Resource ImageChannel allows to connect TxImageLink operators with RxImageLink operators. Each operator TxImageLink needs one resource ImageChannel exclusively. Each resource ImageChannel can be connected to exactly one operator RxImageLink, i.e., a maximum of 1024 TxImageLink and 1024 RxImageLink operators can be used in one design. Resource ImageChannel is visible in the Resources dialog.

Table 45. List of Device Resources LightBridge and microEnable 5 marathon


Shared Memory Concept

The platforms microEnable 5 marathon and LightBridge are assembled with only one physical RAM bank (the size of which is platform-specific). This single physical bank is formatted into 4 non-overlapping memory regions. These 4 regions are represented inside VisualApplets as 4 virtual RAM banks. When an operator reserves a RAM resource, it is using a virtual RAM bank which maps to an exclusive non-overlapping memory region inside the physical RAM.

The RAM bandwidth, however, is shared between all RAM based operators in a design. When a design utilizes all 4 RAM resources, each of the 4 RAM based operators can have up to 1.6 GB/s exclusive bandwidth, minus the efficiency factor of that particular operator. When only one RAM based operator is used in the design, this operator gets the total bandwidth of 6.4 GB/s. When 2 operators are used, each of the two operators gets half the total bandwidth, etc.

[Note] Bandwidth per Operator

The on-board RAM provides 6.4GB/s total bandwidth. The bandwidth available for an individual RAM based operator is the total bandwidth divided by the number of all instantiated RAM based operators in the design.

RAM architecture

Figure 356. RAM architecture


This RAM architecture needs to be considered when designing with RAM based operators.

Due to the shared bandwidth architecture, the applet developer should utilize all 256 bits of the operator’s memory interface (RAM Data Width) to achieve maximal throughput through the memory interface when using multiple RAM based operators even though the single RAM operator needs less bandwidth on its input.